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Please note: Do It Yourself articles and guides are intended for technically advanced users. Please review important cautionary information at the end of this page. Republished articles presented in the Do It Yourself section do not necessarily reflect the opinions or positions of AMD.
A Guide to Memory Timing
The performance and stability of any system depends in part on the memory being used and the settings for the RAM timing. Many users may prefer "xyz" brand, and certainly using brand name memory is a very good idea since low quality memory is often at the root of many stability issues. However, it is also important to pay attention to the timing settings of the memory used.
IMPORTANT: Setting memory timings incorrectly could result in lost or corrupted data (resulting in system instability) or boot/post failure. If a system fails to post, default settings can be restored by clearing the CMOS/BIOS via the clear real time clock jumper on the motherboard. Refer to the board manual for the correct procedure.
The topic of memory architecture is too detailed and complex to cover in a single brief article. We will attempt to simplify a portion of the topic that addresses memory timings and how they work.
Typical timing parameters appear as 2-3-2-6-T1 or some variant. So what do these numbers mean?
Before delving into these specific settings, let's first define some common terms used when discussing memory timings.
- RAS - Row Address Strobe or Row Address Select
- CAS - Column Address Strobe or Column Address Select
- tRAS - Active to precharge delay; this is the delay between the precharge and activation of a row
- tRCD - RAS to CAS Delay; the time required between RAS and CAS access
- tCL - (or CL) CAS Latency
- tRP - RAS Precharge; the time required to switch from one row to the next row, for example, switch internal memory banks
- tCLK – ClocK; the length of a clock cycle
- Command Rate - the delay between Chip Select (CS), or when an IC is selected and the time commands can be issued to the IC
- Latency - The time from when a request is made to when it is answered; the total time required before data can be written to or read from the memory.
Some of the above terms are more important to system stability and performance than others. However, to understand the whole, it is important to understand the role of each of these settings/signals. Therefore, the numbers 2-3-2-6-T1 refer to CL-tRCD-tRP-tRAS-Command Rate and are measured in clock cycles.
tRAS
Memory architecture is like a spreadsheet with row upon row and column upon column, with each row being one bank. For the CPU to access memory, it first must determine which row or bank in the memory is to be accessed and then activate that row with the RAS signal. Once activated, the row can be accessed over and over, until the data is exhausted. This is why tRAS has little effect on overall system performance but could impact system stability if set incorrectly.
tRCD
tRCD is the delay from the time a row is activated to when the cell (or column) is activated via the CAS signal and data can be written to or read from a memory cell. When memory is accessed sequentially, the row is already active and tRCD will not have much impact. However, if memory is not accessed in a linear fashion, the current active row must be deactivated and then a new row selected/activated. In such an example, low tRCD's can improve performance. However, like any other memory timing, putting this too low for the module can cause in instability.
CAS Latency
Certainly, one of the most important timings is the CAS Latency, which is also the one most people understand. Since data is often accessed sequentially (same row), the CPU need only select the next column in the row to get the next piece of data. In other words, CAS Latency is the delay between the CAS signal and the availability of valid data on the data pins (DQ). The latency between column accesses (CAS) then plays an important role in the performance of the memory. The lower the latency, the better the performance. However, the memory modules must be able to support low-latency settings.
tRP
tRP is the time required to terminate one row access and begin the next row access. tRP might also be seen as the delay required between deactivating the current row and selecting the next row. So in conjunction with tRCD, the time required (or clock cycles required) to switch banks (or rows) and select the next cell for reading, writing, or refreshing is a combination of tRP and tRCD.
tRAS
tRAS is the time required before (or delay needed) between the active and precharge commands. In other words, how long the memory must wait before the next memory access can begin.
tCLK
This is simply the clock used for the memory. Note that because frequency is 1/t, if memory were running at 100Mhz, the timing of the memory would be 1/100Mhz, or 10nS.
Command Rate
The Command Rate is the time needed between the chip select signal and when commands can be issued to the RAM module IC. Typically, these are either 1 clock or 2.
This covers much of the basic settings for memory and how they work. As mentioned earlier, it is important to understand what timings your memory will support. Refer to your memory vendor’s website or datasheets for more information.
Cautionary Statement
Activities and projects described herein may involve the use of tools and materials that may present health and safety hazards. These must be handled carefully and all tools and products should be used strictly according to manufacturers' precautions and instructions for the safe use of the respective tool or product. The techniques described herein may result in the voiding of manufacturers' warranties. The user assumes all risks associated with the techniques described in this article/guide. THIS INFORMATION IS PROVIDED “AS IS” WITH NO WARRANTY, EXPRESS OR IMPLIED. AMD ASSUMES NO RESPONSIBILITY FOR ANY ERRORS CONTAINED IN THIS ARTICLE/GUIDE AND HAS NO LIABILITY OR OBLIGATION FOR ANY DAMAGES ARISING FROM OR IN CONNECTION WITH THE USE OF THIS ARTICLE/GUIDE.
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